Since the invention of the integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limit comes from the significant increase in the number and the length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase. Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D IC, two wafers, each including a plurality of semiconductor chips having integrated circuits, are formed. The wafers are then bonded together. Deep vias are then formed to interconnect the integrated circuits in the two wafers.
Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein a plurality of dies is bonded to a wafer. An advantageous feature of the die-to-wafer bonding is that the size of dies may be smaller than the size of chips on the wafer. During a typical die-to-wafer bonding process, spacings will be left between the dies. FIGS. 1 and 2 illustrate cross-sectional views of intermediate stages in a conventional die-to-wafer bonding process. Referring to FIG. 1, dies 100 are stacked on wafer 102, which include semiconductor chips 104. Semiconductor chips 104 are larger than dies 100, and leave spacings 106 between dies 100. During subsequent process steps, as shown in FIG. 2, dies 100 are thinned, for example, to a thickness of about 30 μm, so that through-silicon vias (TSV) 110, which are in dies 100, are exposed. Bond pads (not shown) may then be formed on the surfaces of dies 100 and connected to TSV 110.
The above-discussed die-to-wafer bonding process suffers from drawbacks. During the thinning of dies 100, undesirable substances, such as moisture, particles generated during the thinning, and detrimental chemicals, may fall into spacing 106, and may degrade the performance of semiconductor chips 104. Currently, there are no effective methods for removing the undesirable substances. Further, the existing structure as shown in FIG. 2 has limited number of input/outputs. This is partially because TSV 100 (or other possible conductive feature connected to the subsequently formed bond pads) needs to have pitches great enough to accommodate the bond pads. Further, it is difficult to form metallization layers on dies 100. The equipments for forming dielectric layers, for example, the equipments for chemical vapor deposition, will reject to form films on the surface of the structure shown in FIG. 2, whose top surface is considered to be too rough by the equipments. Therefore, the number of inputs/outputs of the stacked-die structure has been limited to the existing inputs/outputs in dies 100. New die-to-wafer stacking methods are thus needed to solve the above-discussed problems.